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1 m e m o r y all data sheets are subject to change without notice (858) 503-3300 - fax: (858) 503-3301 - www.maxwell.com 12-bit, 41 msps a/d converter 9042 ?2007 maxwell technologies all rights reserved. 01.07.05 rev 7 f eatures : ? total dose hardness: - > 300 krad (si) sel > 120 mev-cm2/mg 41 msps minimum sampling rate 80 db spurious-free dynamic range (sfdr) package: - 28 pin r ad -p ak ? flat pack 595 mw power dissipation single 5 volt power supply on-chip t/h and reference two?s complement output format cmos compatible output levels d escription : maxwell technologies? 9042 12-bit analog-to-digital converter features a greater than 300 krad (si) total dose tolerance. using maxwell?s radiation-hardened r ad -p ak ? packaging technology, the 9042 realizes a higher performance, and low power consumption. all necessary functions, including track- and-hold (t/h) and reference are included on chip to provide a complete conversion solution. the 9042 runs off of a single +5v supply and provides cmos-compatible digital outputs at 41 msps. designed specifically to address the needs of wide- band, multichannel receivers, the 9042 maintains 80 db spuri- ous-free dynamic range (sfdr) over a bandwidth of 20 mhz. noise performance is also exceptional; typical signal to noise ratio is 68 db. maxwell technologies' patented r ad -p ak ? packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding for a lifetime in an orbit or space mission. this product is available with screening up to maxwell technologies self-defined class k.
m e m o r y 2 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 t able 1. 9042 p in d escription p in s ymbol d escription 1 gnd ground 2dv cc 5v power supply (digital) 3 gnd ground 4 encode encode input. data conversion initiated on rising edge. 5 encode complement of encode. drive differently with encode or bypass to ground for single-ended clock mode. 6 gnd ground 7 gnd ground 8 ain analog input. 9v offset voltage offset input. sets mid-point of analog input range. normally tied to v ref through 50 ohm resistor. 10 v ref internal voltage reference. nominally 2.4v; normally tied to v offset through 50 ohm resistor. bypass to ground with 0.01 f capacitor. 11 gnd ground 12 av cc 5v power supply (analog) 13 gnd ground 14 av cc 5v power supply (analog) 15 nc no connects. 16 nc no connects. 17 d0 (lsb) digital output bit (least significant bit). 18 - 27 d1 - d10 digital output bits. 28 d11 (msb) 1 1. output coded as twos compliment digital output bit (most significant bit).
m e m o r y 3 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 t able 2. 9042 a bsolute m aximum r atings 1 1. a bsolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. p arameter s ymbol m in t ypical m ax u nit electrical analog supply voltage av cc 07v digital supply voltage dv cc 07v analog input voltage a in 0.5 4.5 v analog input current 20 ma digital input voltage (encode) 0 av cc v encode, encode differential voltage 4 v digital output current -40 40 ma package weight 5.25 grams thermal impedance jc 2.39 c/w environmental maximum junction temperature t j 150 c operating temperature range t a -55 125 c storage temperature range t s -65 150 c t able 3. d elta l imits p arameter v ariation i(av cc ) 10% of specified value in table 4 i(dv cc ) 10% of specified value in table 4 i cctotal 10% of specified value in table 4 t able 4. 9042 dc e lectrical c haracteristics (av cc = dv cc = +5v 5%; v ref tied to v offset through 50 ? ; t a = -55c to +125c p arameter s ymbol c ondition s ubgroups m in t yp m ax u nit resolution 12 dc accuracy no missing codes 1 -55 to 125c 1, 2, 3 guaranteed offset error -55 to 125c 1, 2, 3 -10 3 10 mv offset tempco -55 to 125c 1, 2, 3 25 ppm/c gain error -55 to 125c 1, 2, 3 -6.5 0 6.5 % fs gain tempco -55 to 125c 1, 2, 3 -50 ppm/c reference out v ref 2 25c 1 2.3 2.4 2.5 v
m e m o r y 4 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 analog input (ain) input voltage range 1, 2, 3 v ref 0.5 v input resistance -55 to 125c 2, 3 200 250 300 ? input capacitance 25c 1 7 encode inputs 1,3 logic compatibility 4 ttl/ cmos logic ?1? voltage v ih -55 to 125c 1, 2, 3 2.0 5.0 v logic ?0? voltage v il -55 to 125c 1, 2, 3 0 0.8 v logic ?1? current (v inh = 5v) i ih -55 to 125c 1, 2, 3 450 625 800 a logic ?0? current (v inl = 0v) i il -55 to 125c 1, 2, 3 -400 -300 -200 a input capacitance 25c 1 2.5 pf digital outputs logic compatibility cmos logic ?1? voltage (i oh = 10 a) v oh 25c 1 3.5 4.2 v -55 to 125c 1, 2, 3 3.5 logic ?0? voltage (i ol = 10 a) v ol 25c,125c 1, 2 -- 0.80 v -55 3 0.90 output coding twos compliment power supply analog supply voltage av cc -55 to 125c 1, 2, 3 5.0 v analog supply current i avcc -55 to 125c 1, 2, 3 -- 160 ma digital supply voltage dv cc -55 to 125c 1, 2, 3 5.0 v digital supply current i dvcc -55 to 125c 1, 2, 3 -- 20 ma supply current (total) i cctotal -55 to 125c 1, 2, 3 119 180 ma power dissipation -55 to 125c 1, 2, 3 595 990 mw power supply rejection psrr 25c 1 -20 1 20 mv/v -55 to 125c 1, 2, 3 5 mv/v differential non-linearity (encode = 20 msps) dnl -55 to 125c 1, 2,3 -1.0 0.3 1.0 lsb integral non-linearity (encode = 20 msps) inl -55 to 125c 1, 2, 3 -1.5 0.75 1.5 lsb 1. guaranteed by design. 2. v ref is normally tied to v offset through 50 ohms. if v ref is used to provide dc offset to other circuits, it should first be buffered 3. encode driven by single-ended source; encode bypassed to ground through 0.01 f capacitor. 4. encode may also be driven differently in conjunction with encode . t able 4. 9042 dc e lectrical c haracteristics (av cc = dv cc = +5v 5%; v ref tied to v offset through 50 ? ; t a = -55c to +125c p arameter s ymbol c ondition s ubgroups m in t yp m ax u nit
m e m o r y 5 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 t able 5. 9042 ac e lectrical c haracteristics 1 (av cc = dv cc = +5v 5%; encode & encode = 41 msps; v ref tied to v offset through 50 ? ; t a = -55c to +125c) p arameter s ymbol c ondition s ubgroups m in t yp m ax u nit signal to noise ratio 2 analog input @ -1 dbfs snr db 1.2 mhz 25c 4 -- 68 -- -55 to 125c 5, 6 -- 67.5 -- 9.6 mhz 25c 4 -- 67.5 -- -55 to 125c 5, 6 -- 67 -- 19.5 mhz 25c 4 64 67 -- -55 to 125c 5, 6 -- 66.5 -- sinad 3 analog input @ -1 dbfs sinad db 1.2 mhz 25c 4 -- 67.5 -- -55 to 125c 5, 6 -- 67 -- 9.6 mhz 25c 4 -- 67.5 -- -55 to 125c 5, 6 -- 67 -- 19.5 mhz 25c 4 64 67 -- -55 to 125c 5, 6 -- 66.5 -- worst spur 4 analog input @ -1 dbfs dbc 1.2 mhz 25c 4 -- 80 -- -55 to 125c 5, 6 -- 78 -- 9.6 mhz 25c 4 -- 80 -- -55 to 125c 5, 6 -- 78 -- 19.5 mhz 25c 4 73 80 -- -55 to 125c 5, 6 -- 78 -- small signal spurios free dynamic range (w/ dither) 5 analog input @ sfdr dbfs 1.2 mhz -55 to 125c 4, 5, 6 -- 90 -- 9.6 mhz -- 90 -- 19.5 mhz -- 90 -- two-tone imd rejection 6 f1, f2 @ -7 dbfs -55 to 125c 4, 5, 6 -- 80 -- dbc two-tone sfdr (w/dither) 7 -55 to 125c 4, 5, 6 -- 90 -- dbfs thermal noise 25c 9 -- 0.33 -- lsb rms analog input bandwidth 8 25c 9 100 mhz transient response 8 25c 9 10 ns overvoltage recovery time 8 25c 9 25 ns
m e m o r y 6 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 1. t iming d iagram maximum conversion rate -55 to 125c 9, 10, 11 41 msps minimum conversion rate 8 -55 to 125c 9, 10, 11 5 msps aperature delay t a 25c 9 -250 ps aperature uncertainty jitter 25c 9 0.7 ps rms encode pulse width high 25c 9 10 ns encode pulse width low 25c 9 10 ns output delay t od -55 to 125c 9, 10, 11 5 9 14 ns 1. all ac specifications tested by driving encode and encode differentially. 2. analog input signal power at -1 dbfs; signal-to-noise ratio (snr) is the ratio of signal level to total noise (first five har monics removed). 3. analog input signal power at -1 dbfs; signal-to-noise and distorsion (sinad) is the ratio of signal level to total noise + ha rmonics. 4. analog input signal power at -1 dbfs; worst spur is the ratio of signal level to worst spur, usually limited by harmonics. 5. analog input signal power swept from -20 dbfs to -95 dbfs; dither power = -32.5 dbm; dither circuit used on input signal sfdr is ratio of converter full scale to worst spur. 6. tones at -7dbfs (f1 = 15.3 mhz, f2 = 19.5 mhz); two tone intermodualtion distortion (imd) rejection is ratio or either tone t o worst third order intermod product. 7. both input tones swept from -20 to -95 dbfs; dither power = -32.5 dbm; dither circuit used on input signal two-tone spurious- free dynamic range (sfdr) is the ratio of converter full scale to worst spur. 8. guaranteed by design. t able 5. 9042 ac e lectrical c haracteristics 1 (av cc = dv cc = +5v 5%; encode & encode = 41 msps; v ref tied to v offset through 50 ? ; t a = -55c to +125c) p arameter s ymbol c ondition s ubgroups m in t yp m ax u nit
m e m o r y 7 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 2. a nalog i nput s tage e quivalent c ircuit f igure 3. e ncode i nputs e quivalent c ircuit
m e m o r y 8 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 4. c ompensation p in , c1 e quivalent c ircuit
m e m o r y 9 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 5. d igital o utput s tage e quivalent c ircuit f igure 6. 2.4 v r eference e quivalent c ircuit
m e m o r y 10 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 7. s ingle t one at 1.2 mh z f igure 8. s ingle t one at 9.6 mh z
m e m o r y 11 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 9. s ingle t one at 19.5 mh z f igure 10. h armonics vs . ain
m e m o r y 12 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 11. n oise vs . ain f igure 12. h armonics vs . ain
m e m o r y 13 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 13. t wo t ones at 15.3 mh z and 19.5 mh z f igure 14. s ingle t one sfdr
m e m o r y 14 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 15. t wo t ones sfdr f igure 16. snr w orst h armonic vs . e ncode
m e m o r y 15 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 f igure 17. snr w orst c ase s purious vs . d uty c ycle f igure 18. npr o utput s pectrum
m e m o r y 16 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 theory of operation the 9042 analog-to-digital converter (adc) employs a twostage subrange architecture. this design approach ensures 12-bit accuracy, without the need for laser trim, at low power. as shown in the functional block diagram, the 1 v p-p singleended analog input, centered at 2.4 v, drives a single-in to differential-out amplifier, a1. the output of a1 drives the first track-and-hold, th1. the high state of the encode pulse places th1 in hold mode. the held value of th1 is applied to the input of the 6-bit coarse adc. the digital output of the coarse adc drives a 6-bit dac; the dac is 12 bits accurate. the output of the 6-bit dac is subtracted from the delayed analog signal at the input to th3 to generate a residue signal. th2 is used as an analog pipeline to null out the digital delay of the coarse adc. the residue signal is passed to th3 on a subsequent clock cycle where the signal is amplified by the residue amplifier, a2, and converted to a digital word by the 7-bit residue adc. one bit of overlap is used to accommodate any linearity errors in the coarse adc. the 6-bit coarse adc word and 7-bit residue word are added together and corrected in the digital error correction logic to generate the output word. the result is a 12-bit parallel digital word which is cmos-compatible, coded as twos com- plement. applying the 9042 encoding the 9042 the 9042 is designed to interface with ttl and cmos logic families. the source used to drive the encode pin(s) must be clean and free from jitter. sources with excessive jitter will limit snr (ref. equation 1 under ?noise floor and snr?). figure 19. single-ended ttl/cmos encode
m e m o r y 17 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 the 9042 encode inputs are connected to a differential input stage (see figure 3). with no input connected to either the encode or input, the voltage dividers bias the inputs to 1.6 volts. for ttl or cmos usage, the encode source should be connected to encode. encode should be decoupled using a low inductance or microwave chip capacitor to ground. devices such as avx 05085c103ma15, a 0.01 mf capacitor, work well. if a logic threshold other than the nominal 1.6 v is required, the following equations show how to use an external resis- tor, rx, to raise or lower the trip point (see figure 3; r1 = 17k, r2 = 8k). to lower logic threshold. figure 20. lower logic threshold for encode to raise logic threshold.
m e m o r y 18 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 figure 21. raise logic threshold for encode while the single-ended encode will work well for many applications, driving the encode differentially will provide increased performance. depending on circuit layout and system noise, a 1 db to 3 db improvement in snr can be realized. it is not recommended that differential ttl logic be used however, because most ttl families that support complementary outputs are not delay or slew rate matched. instead, it is recommended that the encode signal be ac- coupled into the encode and encode pins. the simplest option is shown below. the low jitter ttl signal is coupled with a limiting resistor, typically 100 ohms, to the primary side of an rf transformer (these transformers are inexpensive and readily available; part# in figure 22 is from mini-circuits). the secondary side is connected to the encode and encode pins of the converter. since both encode inputs are self biased, no additional components are required. figure 22. ttl source ? differential encode
m e m o r y 19 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 if no ttl source is available, a clean sine wave may be substituted. in the case of the sine source, the matching net- work is shown below. since the matching transformer specified is a 1:1 impedance ratio, r, the load resistor should be selected to match the source impedance. the input impedance of the 9042 is negligible in most cases. figure 23. sine source ? differential encode if a low jitter ecl clock is available, another option is to accouple a differential ecl signal to the encode input pins as shown below. the capacitors shown here should be chip capacitors but do not need to be of the low inductance vari- ety. figure 24. differential ecl for encode
m e m o r y 20 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 as a final alternative, the ecl gate may be replaced by an ecl comparator. the input to the comparator could then be a logic signal or a sine signal. figure 25. ecl comparator for encode care should be taken not to overdrive the encode input pin when ac coupled. although the input circuitry is electrically protected from over or under voltage conditions, improper circuit operations may result from overdriving the encode input pins. driving the analog input because the 9042 operates off of a single +5 v supply, the analog input range is offset from ground by 2.4 volts. the analog input, ain, is an operational amplifier configured in an inverting mode (ref. equivalent circuits: analog input stage). voffset is the noninverting input which is normally tied through a 50 ohm resistor to vref (ref. equivalent circuits: 2.4 v reference). since the operational amplifier forces its inputs to the same voltage, the inverting input is also at 2.4 volts. therefore, the analog input has a thevenin equivalent of 250 ohms in series with a 2.4 volt source. it is strongly recommended that the 9042?s internal voltage reference be used for the amplifier offset; this reference is designed to track internal circuit shifts over temperature.
m e m o r y 21 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 figure 26. analog input offset by +2.4 v reference although the 9042 may be used in many applications, it was specifically designed for communications systems which must digitize wide signal bandwidths. as such, the analog input was designed to be ac-coupled. since most communi- cations products do not down-convert to dc, this should not pose a problem. one example of a typical analog input cir- cuit is shown below. in this application, the analog input is coupled with a high quality chip capacitor, the value of which can be chosen to provide a low frequency cutoff that is consistent with the signal being sampled; in most cases, a 0.1 mf chip capacitor will work well. figure 27. ac-coupled analog input signal
m e m o r y 22 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 another option for ac-coupling is a transformer. the impedance ratio and frequency characteristics of the transformer are determined by examining the characteristics of the input signal source (transformer primary connection), and the 9042 input characteristics (transformer secondary connection). ?rt? should be chosen to satisfy termination require- ments of thesource, given the transformer turns ratio. a blocking capacitor is required to prevent 9042 dc bias currents from flowing through the transformer. figure 28. transformer-coupled analog input signal when calculating the proper termination resistor, note that the external load resistor is in parallel with the 9042 analog input resistance, 250 ohms. the external resistor value can be calculated from the following equation: where z is desired impedance. 9042 a dc-coupled input configuration (shown below) is limited by the drive amplifier performance. the 9042?s on-chip refer- ence is buffered using the op279 dual, rail-to-rail operational amplifier. the resulting voltage is combined with the analog source using an ad9631. pending improvements in drive amplifiers, this dc-coupled approach is limited to ~75 db?80 db of dynamic performance depending on which drive amplifier is used. the ad9631 and op279 run off 5 v. figure 29. dc-coupled analog input circuit
m e m o r y 23 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 power supplies care should be taken when selecting a power source. linear supplies are strongly recommended as switching sup- plies tend to have radiated components that may be ?received? by the 9042. each of the power supply pins should be decoupled as closely to the package as possible using 0.1 mf chip capacitors. the 9042 has separate digital and ana- log +5 v pins. the analog supplies and the denoted a vcc digital supply pins are denoted d vcc . although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. this is because the fast digital output swings can couple switching noise back into the analog supplies. note that a vcc must be held within 5% of 5 volts, however the d vcc supply may be varied according to output digital logic family (i.e., d vcc should be connected to the supply for the digital circuitry). output loading care must be taken when designing the data receivers for the ad9042. it is recommended that the digital outputs drive a series resistor of 499 ohms followed by a cmos gate like the 74ac574. to minimize capacitive loading, there should only be one gate on each output pin. the digital outputs of the 9042 have a unique constant slew rate output stage. the output slew rate is about 1 v/ns independent of output loading. a typical cmos gate combined with pcb trace and through hole will have a load of approximately 10 pf. therefore as each bit switches, 10 ma of dynamic current per bit will flow in or out of the device. a full- scale transition can cause up to 120 ma (12bits 10 ma/bit) of current to flow through the digital output stage. the series resistor will minimize the output currents that can flow in the output stage. these switching currents are confined between ground and the d vcc pin. standard ttl gates should be avoided since they can appreciably add to the dynamic switching currents of the 9042.
m e m o r y 24 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 note: all dimensions in inches 28-p in r ad -p ak ? f lat p ackage s ymbol d imension m in n om m ax a 0.129 0.142 0.155 b 0.015 0.017 0.022 c 0.004 0.005 0.009 d -- 0.820 0.828 e 0.474 0.480 0.486 e1 -- -- 0.506 e2 0.255 0.260 -- e3 0.000 0.110 -- e 0.050 bsc l 0.375 0.385 0.395 q 0.021 0.025 0.029 s1 0.000 0.077 -- n28
m e m o r y 25 all data sheets are subject to change without notice ?2005 maxwell technologies all rights reserved. 12-bit, 41 msps a/d converter 9042 01.07.05 rev 7 important notice: these data sheets are created using the chip manufacturer?s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the use of this information. maxwell technologies? products are not authorized for use as critical components in life support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.

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